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preliminary information ? 1998 vertex networks, inc. 1 rev. 4.5 ? february 1999 distinctive characteristics t highly integrated central switch contro l ler t state of the art 0.35 micron 3.3 volt cmos process t 256-pin pqfp package t operating frequency -40 40 mhz maximum -50 50 mhz maximum -66 66 mhz maximum t 16-bit external cam interface supports ?k to 16k mac a d dresses t 32-bit control buffer memory inte r face supports 128k to 1m bytes utilize high performance 32-bit sy n - chronous burst sram t hardware assisted buffer and queue ma n - agement to minimize cpu ove r head t 32-bit management bus i/o inte r face allows host to access cam and control buffer memory supports big and little endian cpus direct interface with various different standard microprocessors including 386, 486 families and motorola mpc s e - ries embedded processors t 32-bit xpressflow bus inte r face switching bandwidth - 1.28 gbps @ 40 mhz system clock - 1.60 gbps @ 50 mhz system clock - 2.10 gbps @ 66.67 mhz system clock supports up to 8 multi-port network a c - cess contro l lers xpressflow bus access arbitr a tion xpressflow bus data transfer load regul a tion t full ip switching addresses resolved by sc220 t mac address mapping table supports either cam based or sram based switching data base sc220 ? xpressflow e n gine xpressflow 2020 ethernet routing switch chipset control buffer memory xpressflow bus xpressflow bus 32 32 32 sc220 xpressflow engine address mapping table 16 cam (optional) sc220 - xpressflow engine general description the xpressflow engine contains the switching data base i n - terface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. hardware assisted queue manager is incorporated to facilitate buffer management. it also provides a generic management bus interface to allow external processor to do initialization, learning, vlan, and rmon support, etc. in addition, a xpressflow bus interface block is responsible for communicating with the network access controllers through the xpressflow message passing protocol. related components: t ea218e ? 8-port 10mbps ethernet a c cess controller t ea218 ? 6-port 10 + 2-port 10/100 ethernet access co n troller t ea234 ? 4-port 10/100 fast ethernet
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow e n gine ? 1998 vertex networks, inc. 2 rev. 4.5 ? february 1999 characteristics continue t built-in address to port res o lution embedded 32-bit hisc? (high density instruction set core) pro c essor optimized architecture for switch appl i - cations loadable firmware for easy u p grade t supports unicast, multicast, and broadcast frames t address filtering destination & source mac address matching & filtering t vlan classification & verif i cation up to 62 groups level 1 and 2 mapping vlan id tagging & stri p ping auto padding if necessary after stripping t supports store-&-forward frame forwar d - ing mode t collects statistics for rmon control buffer memory management-bus xpressflow bus xpressflow bus interafce 32 32 32 automatic buffer manager mngmt bus interface 32 32 control buffer memory interface hisc i/o registers 32 cam interface address mapping table 32 32 16 hisc core 32 16 32 32 32 cam sram 16 sc220 xpressflow engine block diagram ? sc220 xpressflow engine typical application : a 16-port ethernet switch with 4-fast ethernet address mapping table flash rom sc220 x pressflow engine ea208e 8-port ethernet access controller management bus buffer ram switch manager cpu dram rs232 local control console buffer ram 8 ethernet ports buffer ram 8 ethernet ports xpressflow bus ea208e 8-port ethernet access controller buffer ram four 100m fast ethernet ports ea234 4-port ethernet access controller system block diagram -- 16-port ethernet switch with 4 fast ethernet up-links
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 3 rev. 4.5 ? february 1999 1. pin assignment 1.1 logic symbol sc220 t_mode c_d[15:0] c_ce# c_we# c_cm# c_ec# c_mf# c_ff# cam interface test pin s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_ovld# 8 8 s_hpreq# s_req[8:1]# s_gnt[8:1]# s_clk xpressflow bus interface management bus interface p_d[31:0] p_cs# p_ads# p_rwc p_rdy# p_bs16# p_int p_a[11:1] p_rstin# p_rstout p_clk l_d[31:0] l_oe[3:0]# l_adsc# l_clk l_a[18:2] l_we[3:0]# l_bwe[3:0]# 4 4 control buffer memory interface 4 note: the sc220 is pin compatible to the sc201 with only one exception: the rstout pin of sc201 is defined as a synchronous reset output pin which follows the rstin input and re-synchronous with p_clk for meeting the 80386 timing requirement. the rstout pin for sc220 has a totally different function. it is no longer related with the rstin input. the rstout is a watc h - dog output from sc220 to keep track of the active state of the host processor. host processor needs to access the keep alive register periodically to prevent the setting of the rstout output. the rstout output can be use as reset input to the host processor.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 4 rev. 4.5 ? february 1999 1.2 pin assignment ( preliminary ) note: # active low signal input input signal i-st input signal with schmitt-trigger output output signal (tri-state driver) out-od output signal with open-drain driver i/o-ts input & output signal with tri-state driver i/o-od input & output signal with open-drain driver 5vt input with 5v tolerance pin no(s). sy m bol type name & functions xpressflow bus inte r face 122,121,119,118, 116 s_d[31:27] / p_c[0:4] cmos i/o-ts xpressflow bus ? data bit [31:28] or processor interface configuration bit [0:4] 114,113,111,109,108, 106,105,104,103,101, 100,98,97,96,95,93,92, 90,89,88,87,85,84,82, 80,79,77 s_d[26:0] cmos i/o-ts xpressflow bus ? data bit [27:0] 71 s_msgen# cmos i/o-ts xpressflow bus ? message e n velope 69 s_eof# cmos i/o-ts xpressflow bus ? end of frame 72 s_irdy cmos i/o-ts xpressflow bus ? initiator ready 70 s_tabt# cmos i/o-od xpressflow bus ? target abort 123 s_hpreq# cmos i/o-od xpressflow bus ? high priority r e quest 140,138,135,133,131, 129,126,124 s_req[8:1]# cmos input ** xpressflow bus ? bus request [8:1] 141,139,137,134,132, 130,128,125 s_gnt[8:1]# cmos output xpressflow bus ? bus grant [8:1] 73 s_ovld# cmos output xpressflow bus ? bus overload 75 s_clk cmos i n put xpressflow bus ? clock
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 5 rev. 4.5 ? february 1999 pin no(s). sy m bol type name & functions xpressflow bus inte r face 185,184,183,182,180, 179,177,176,175,174, 172,171,169,168,167, 166,164,163,160,159, 157,156,154,153,151, 150,149,148,146,145, 143,142 p_d[31:0] ttl i/o-ts (5vt) management bus ? data bit [31:0] 211,210,208,207,205, 204,203,202,201,199, 198 p_a[11:1] ttl input (5vt) management bus ? address bit [11:1] 196 p_ads# ttl input (5vt) management bus ? address strobe 191 p_rwc ttl input (5vt) management bus ? read/write co n trol 183 p_rdy# cmos out- od management bus ? data ready 184 p_bs16# cmos out- od management bus ? 16 bit data bus 185 p_cs# ttl input (5vt) management bus ? chip select 189 p_rstin# ttl in-st (5vt) system reset input 190 p_rstout cmos ou t put cpu reset output 192 p_int cmos ou t put management bus ? interrupt r e quest 187 p_clk ttl input (5vt) cpu clock control buffer memory inte r face 60,59,58,57,56,54,53,51, 50,49,48,47,46,45,43,42, 40,39,38,37,36,34,33,30, 29,27,26,25,24,23,22,21, l_d[31:0] ttl i/o-ts local memory bus ? data bit [31:0] 8,6,5,3,2,1,256,255,254, 253,251,250,248,247, 246,245,244 l_a[18:2] cmos ou t put local memory bus ? address bit [17:2] 9 l_a[19] / l_oe[3]# cmos ou t put local memory bus ? address bit [19:18] or memory read chip select [3] 63, 11, 19 l_oe[2:0]# cmos ou t put local memory bus- read chip select [2:0] 242, 62, 10, 18 l_we[3:0]#, cmos ou t put local memory bus ? write chip select [3:0] 12,13,14,15 l_bwe[3:0]# cmos ou t put local memory bus ? byte write enable [3:0] 16 l_adsc# cmos ou t put local memory bus ? controller address status 66 l_clk cmos ou t put local memory bus ? synchronous clock
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 6 rev. 4.5 ? february 1999 pin no(s). sy m bol type name & functions cam inte r face 214,215,217,218,219, 220,221,222,223,225, 226,228,229,220.221, c_d[15:0] ttl i/o-ts (5vt) cam interface ? data bus bit [15:0] 239 c_we# cmos ou t put cam interface ? write enable 241 c_ce# cmos ou t put cam interface ? chip enable 233 c_ec# cmos ou t put cam interface ? enable co m parison 234 c_cm# cmos ou t put cam interface ? data/command select 236 c_ff# ttl input (5vt) cam interface ? full flag 237 c_mf# ttl input (5vt) cam interface ? match flag test & reserved pins 65 test cmos i/o-ts test pin ? set test mode upon reset, and provides test status output during test mode 62,63,64,67,242 n/c --- reserved pins (5 pins) power pins 32,78,115,161,206,243 vdd (core) input +3.3 volt dc supply for core logic (6 pins) 7,20,31,44,55,68,76,86, 94,102,110,120,144, 152,162,170,178,186, 197,216,227,238,252 vdd input +3.3 volt dc supply for i/o pads (23 pins) 35,81,112,158,209,240 vss (core) input ground for core logic (6 pins) 4,17,28,41,52,61,66,74, 83,91,99,197,117,127, 136,147,155,165,173, 181,188,200,213,224, 235,249 vss input ground for i/o pads (26 pins)
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 7 rev. 4.5 ? february 1999 1.1 1.2 1.3 connection diagram ? 256-pqfp package (top view) pin 1 i.d. 128 129 192 193 256 1 64 65 t_mode vss l_clk vdd s_eof# s_tabt# s_msgen# s_irdy s_ovld# vss s_clk vdd s_d[0] vdd (core) s_d[1] s_d[2] vss (core) s_d[3] vss s_d[4] s_d[5] vdd s_d[6] s_d[7] s_d[8] s_d[9] vss s_d[10] s_d[11] vdd s_d[12] s_d[13] s_d[14] s_d[15] vss s_d[16] s_d[17] vdd s_d[18] s_d[19] s_d[20] s_d[21] vss s_d[22] s_d[23] vdd s_d[24] vss (core) s_d[25] s_d[26] vdd (core) s_d[27] vss s_d[28] / p_c[3] s_d[29] / p_c[2] vdd s_d[30] / p_c[1] s_d[31] / p_c[0] s_hpreq# s_req[1]# s_gnt[1]# s_req[2]# vss s_gnt[2]# p_int p_rwc p_rstout p_rstin# vss p_clk vdd p_d[31] p_d[30] p_d[29] p_d[28] vss p_d[27] p_d[26] vdd p_d[24] p_d[25] p_d[23] p_d[22] vss p_d[21] p_d[20] vdd p_d[19] p_d[18] p_d[17] p_d[16] vss p_d[15] p_d[14] vdd vdd (core) p_d[13] p_d[12] vss (core) p_d[11] p_d[10] vss p_d[9] p_d[8] vdd p_d[7] p_d[6] p_d[5] p_d[4] vss p_d[3] p_d[2] vdd p_d[1] p_d[0] s_gnt[8]# s_req[8]# s_gnt[7]# s_req[7]# s_gnt[6]# vss s_req[6]# s_gnt[5]# s_req[5]# s_gnt[4]# s_req[4]# s_gnt[3]# s_req[3]# xpressflow bus interface test control buffer memory interface cam interface management bus interface l_a[13] l_a[14] l_a[15] vss l_a[16] l_a[17] vdd l_a[18] l_a[19] / l_oe[3]# l_we[1]# l_oe[1]# l_bwe[3]# l_bwe[2]# l_bwe[1]# l_bwe[0]# l_adsc# vss l_we[0]# l_oe[0]# vdd l_d[0] l_d[1] l_d[2] l_d[3] l_d[4] l_d[5] l_d[6] vss l_d[7] l_d[8] vdd vdd (core) l_d[9] l_d[10] vss (core) l_d[11] l_d[12] l_d[13] l_d[14] l_d[15] vss l_d[16] l_d[17] vdd l_d[18] l_d[19] l_d[20] l_d[21] l_d[22] l_d[23] l_d[24] vss l_d[25] l_d[26] vdd l_d[27] l_d[28] l_d[29] l_d[30] l_d[31] vss l_we[2]# l_oe[2]# l_a[12] l_a[11] l_a[10] l_a[9] vdd l_a[8] l_a[7] l_a[6] vss l_a[5] l_a[4] l_a[3] l_a[2] vdd (core) l_we[3]# c_ce# vss (core) c_we# vdd c_mf# c_ff# vss c_cm# c_ec# c_d[0] c_d[1] c_d[2] c_d[3] c_d[4] vdd c_d[5] c_d[6] vss c_d[7] c_d[8] c_d[9] c_d[10] c_d[11] c_d[12] c_d[13] vdd c_d[14] c_d[15] vss p_a[11] p_a[10] vss (core) p_a[9] p_a[8] vdd (core) p_a[7] p_a[6] p_a[5] p_a[4] p_a[3] vss p_a[2] p_a[1] vdd p_ads# p_cs# p_bs16# p_rdy#
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 8 rev. 4.5 ? february 1999 1.4 connection diagram ? 256-bga package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a l_a [13] l_a [12] l_a [10] l_a[5] / p_c[3] l_a[2] / p_c[0] c_ mf# c_ ec# c_d [2] c_d [3] c_d [6] c_d [10] c_d [13] p_a [11] p_a [8] p_a [6] p_a [3] p_ bs16# p_ rdy# b l_a [14] l_a [11] l_a [8] l_a [6] l_a[3] / p_c[1] c_ ce# c_ cm# c_d [1] c_d [4] c_d [7] c_d [11] c_d [14] p_a [10] p_a [7] p_a [4] p_ ads# p_a [2] p_ int c l_a [18] l_a [16] l_a [15] l_a [9] l_a [7] l_a[4] / p_c[2] l_we [3] c_ we# c_ ff# c_d [0] c_d [5] c_d [9] c_d [12] c_d [15] p_a [9] p_a [5] p_a [1] p_ cs# p_ rwc p_rst out d l_oe [1]# l_oe [3]# l_a [17] vdd (core) vss vdd vss vdd vss vss c_d [8] vdd vss vdd vdd (core) vss vdd p_rst in# p_ clk e l_bwe [2]# l_bwe [3]# l_we [1]# vss vss p_d [31] p_d [30] f l_ adsc# l_bwe [0]# l_bwe [1]# vdd vdd p_d [29] p_d [28] p_d [27] g l_d [0] l_oe [0]# vss vdd (core) p_d [26] p_d [25] p_d [24] h l_d [3] l_d [2] l_d [1] l_we [0]# vss p_d [23] p_d [22] p_d [21] j l_d [7] l_d [6] l_d [4] l_d [5] vdd p_d [20] p_d [19] p_d [18] k l_d [9] l_d [8] vdd vss p_d [17] p_d [16] p_d [15] l l_d [10] l_d [11] l_d [12] vss p_d [12] p_d [13] p_d [14] m l_d [13] l_d [14] l_d [15] vdd (core) vss p_d [9] p_d [10] p_d [11] n l_d [16] l_d [17] l_d [18] vss p_d [3] p_d [6] p_d [7] p_d [8] p l_d [19] l_d [20] l_d [21] vdd vdd (core) p_d [2] p_d [4] p_d [5] r l_d [22] l_d [23] l_d [24] l_d [26] vdd p_d [0] p_d [1] t l_d [25] l_d [27] l_d [28] vss vss s_req [7]# s_req [8]# s_gnt [8]# u l_d [29] l_d [30] l_d [31] vdd vss s_d [4] vss vdd vdd (core) vss vdd vss s_d [25] s_d [29] s_req [1]# s_gnt [4]# s_gnt [5]# s_gnt [6]# s_gnt [7]# v l_we [2]# l_ clk s_ tabt# s_d [0] s_d [3] s_d [7] s_d [10] s_d [13] vdd s_d [20] s_d [23] s_d [26] vdd s_d [30] vdd s_req [4]# s_req [5]# w l_oe [2]# s_msg en# s_ eof# s_ ovld# s_d [1] s_d [5] s_d [8] s_d [11] s_d [14] s_d [17] s_d [19] s_d [22] vss s_d [27] s_hp req# s_gnt [1]# s_req [6]# s_gnt [3]# y t_ mode s_ irdy s_ clk s_d [2] s_d [6] s_d [9] s_d [12] s_d [15] s_d [16] s_d [18] s_d [21] s_d [24] s_d [28] s_d [31] s_req [2]# s_gnt [2]# s_req [3]#
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 9 rev. 4.5 ? february 1999 1.5 pin reference table: (256 pin pqfp& 256-bga) pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 l_a[13] 65 test 129 s_req[3]# 193 p_rdy# 2 l_a[14] 66 vss 130 s_gnt[3]# 194 p_bs16# 3 l_a[15] 67 l_clk 131 s_req[4]# 195 p_cs# 4 vss 68 vdd 132 s_gnt[4]# 196 p_ads# 5 l_a[16] 69 s_eof# 133 s_req[5]# 197 vdd 6 l_a[17] 70 s_tabt# 134 s_gnt[5]# 198 p_a[1] 7 vdd 71 s_msgen# 135 s_req[6]# 199 p_a[2] 8 l_a[18] 72 s_irdy 136 vss 200 vss 9 l_a[19] / l_oe[3]# 73 s_ovld# 137 s_gnt[6]# 201 p_a[3] 10 l_we[1]# 74 vss 138 s_req[7]# 202 p_a[4] 11 l_oe[1]# 75 s_clk 139 s_gnt[7]# 203 p_a[5] 12 l_bwe[3]# 76 vdd 140 s_req[8]# 204 p_a[6] 13 l_bwe[2]# 77 s_d[0] 141 s_gnt[8]# 205 p_a[7] 14 l_bwe[1]# 78 vdd (core) 142 p_d[0] 206 vdd (core) 15 l_bwe[0]# 79 s_d[1] 143 p_d[1] 207 p_a[8] 16 l_adsc# 80 s_d[2] 144 vdd 208 p_a[9] 17 vss 81 vss (core) 145 p_d[2] 209 vss (core) 18 l_we[0]# 82 s_d[3] 146 p_d[3] 210 p_a[10] 19 l_oe[0]# 83 vss 147 vss 211 p_a[11] 20 vdd 84 s_d[4] 148 p_d[4] 212 21 l_d[0] 85 s_d[5] 149 p_d[5] 213 vss 22 l_d[1] 86 vdd 150 p_d[6] 214 c_d[15] 23 l_d[2] 87 s_d[6] 151 p_d[7] 215 c_d[14] 24 l_d[3] 88 s_d[7] 152 vdd 216 vdd 25 l_d[4] 89 s_d[8] 153 p_d[8] 217 c_d[13] 26 l_d[5] 90 s_d[9] 154 p_d[9] 218 c_d[12] 27 l_d[6] 91 vss 155 vss 219 c_d[11] 28 vss 92 s_d[10] 156 p _d[10] 220 c_d[10] 29 l_d[7] 93 s_d[11] 157 p_d[11] 221 c_d[9] 30 l_d[8] 94 vdd 158 vss (core) 222 c_d[8] 31 vdd 95 s_d[12] 159 p_d[12] 223 c_d[7] 32 vdd (core) 96 s_d[13] 160 p_d[13] 224 vss 33 l_d[9] 97 s_d[14] 161 vdd (core) 225 c_d[6] 34 l_d[10] 98 s_d[15] 162 vdd 226 c_d[5] 35 vss (core) 99 vss 163 p_d[14] 227 vdd 36 l_d[11] 100 s_d[16] 164 p_d[15] 228 c_d[4] 37 l_d[12] 101 s_d[17] 165 vss 229 c_d[3] 38 l_d[13] 102 vdd 166 p_d[16] 230 c_d[2] 39 l_d[14] 103 s_d[18] 167 p_d[17] 231 c_d[1] 40 l_d[15] 104 s_d[19] 168 p_d[18] 232 c_d[0] 41 vss 105 s_d[20] 169 p_d[19] 233 c_ec# 42 l_d[16] 106 s_d[21] 170 vdd 234 c_cm# 43 l_d[17] 107 vss 171 p_d[20] 235 vss 44 vdd 108 s_d[22] 172 p_d[21] 236 c_ff# 45 l_d[18] 109 s_d[23] 173 vss 237 c_mf# 46 l_d[19] 110 vdd 174 p_d[22] 238 vdd 47 l_d[20] 111 s_d[24] 175 p_d[23] 239 c_we# 48 l_d[21] 112 vss (core) 176 p_d[24] 240 vss (core) 49 l_d[22] 113 s_d[25] 177 p_d[25] 241 c_ce# 50 l_d[23] 114 s_d[26] 178 vdd 242 l_we[3] 51 l_d[24] 115 vdd (core) 179 p_d[26] 243 vdd (core) 52 vss 116 s_d[27] 180 p_d[27] 244 l_a[2] / p_c[0] 53 l_d[25] 117 vss 181 vss 245 l_a[3] / p_c[1] 54 l_d[26] 118 s_d[28] 182 p_d[28] 246 l_a[4] / p_c[2] 55 vdd 119 s_d[29] 183 p_d[29] 247 l_a[5] / p_c[3] 56 l_d[27] 120 vdd 184 p_d[30] 248 l_a[6] 57 l_d[28] 121 s_d[30] 185 p_d[31] 249 vss 58 l_d[29] 122 s_d[31] 186 vdd 250 l_a[7] 59 l_d[30] 123 s_hpreq# 187 p_clk 251 l_a[8] 60 l_d[31] 124 s_req[1]# 188 vss 252 vdd 61 vss 125 s_gnt[1]# 189 p_rstin# 253 l_a[9] 62 l_we[2]# 126 s_req[2]# 190 p_rstout 254 l_a[10] 63 l_oe[2]# 127 vss 191 p_rwc 255 l_a[11] 64 128 s_gnt[2]# 192 p_int 256 l_a[12]
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 10 rev. 4.5 ? february 1999 note: ? for 256-bga package: f4, k4, p4, u5, u9, u12, v11, v15, v17, r17, j17, f17, d17, d14, d12, d8 and d6 are vdd. ? for 256-bga package: d4, m4, u10, p17, g17 and d15 are vdd(core). ? for 256-bga package: e4, g4, l4, n4, t4, u6, u8, u11, u13, w14, t17, m17, k17, h17, e17, d16, d13, d10, d9, d7, and d5 are vss.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 11 rev. 4.5 ? february 1999 2 functional description 2.1 cam interface t direct interface with music mu9c1480 1k x 64 bit content addressable memory (cam) expandable to support 8k mac a d dresses t two access masters: hisc in xpressflow engine, and switch manager cpu t master interface with cam interface logic via two dedicated cam command blocks one for hisc one for switch manager cpu t both hisc and switch manager cpu can a c - cess the cam by setting up their corresponding cam command blocks, and read the return inform a - tion from their own response data block 2.1.1 pin description sy m bol type name & functions c_d[15:0] ttl i/o-ts cam data bus bit [15:0] ? a 16-bit data bus for data/command i n - put/output. c_ce# cmos ou t put cam chip enable ? enables the cam by registers the control signals on its falling edge and release them on its rising edge. also used for loc k ing and unlocking the cascaded daisy chain. c_we# cmos ou t put cam write enable ? allows to write data or command to cam c_cm# cmos ou t put cam data/command select ? defines data or command operations c_ec# cmos ou t put cam enable comparison ? latches and enables the mf and ff outputs during a comparison cycle. c_mf# ttl input cam match flag ? indicates a valid match during a comparison c y cle. c_ff# ttl input cam full flag ? indicates there is no empty location in the cam. cam cam interface logic command block response data block command block response data block from hisc to hisc to cpu from cpu block diagram ? cam interface
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 12 rev. 4.5 ? february 1999 2.1.2 bus cycle waveforms write mac address byte 0, & 1 write mac address byte 2, & 3 write mac address byte 4, & 5 read mac control buffer pointer s_clk c_ce# c_cm# c_ec# c_we# c_mf# c_d[15:0] typical mac address compare operation note: refer to music mu9c1480 cam data sheet for detailed timing p a rameters.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 13 rev. 4.5 ? february 1999 2.2 local memory (control buffer memory) interface t uses industry standard sy n chronous burst sram (pipe-lined mode) supports 64k x 32, 128k x 32, or 256k x 32 chips up to maximum 2m bytes t provides 4 individual byte write enable co n trols t supports back to back read or write oper a tions 2.2.1 pin description symbol type name & functions l_d[31:0] ttl i/o-ts local memory data bus bit [31:0] ? a 32-bit synchronous data bus. l_a[18:2] cmos output local memory address bus bit [18:2] ? bit [17:2] of a synchronous a d - dress bus. the memory address is sampled when l_cs# is enabled and l_adsc# is a s serted. l_a[19] / l_we[3]# cmos output local memory address bus bit [19] or local memory write chip select [3] ? depends on memory configuration, this pin can be used as the local memory address bit [19] or as the local memory write chip select [3]. l_we[2:0]# cmos output local memory write chip select [2:0] ? allows up to write one of the 4 banks of memory. l_oe[3:0]# cmos output local memory read chip select [3:0] ? allows up to read one of the 4 banks of memory. l_bwe[3:0]# cmos output local memory byte write enable [3:0] ? use to write individual bytes. l_adsc# cmos output local memory controller address status ? to load a new address. l_clk cmos output local memory clock ? a synchronous clock to memory devices.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 14 rev. 4.5 ? february 1999 supported memory configurations read/write chip select and high address bits chip #3 chip #2 chip #1 chip #0 ram chip size # of ram chips total buffer memory size l_a[19] / l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 64k x 32 1 256k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 512k bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 1m bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 128k x 32 1 256k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 1m bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 2m bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 256k x32 1 1m bytes l_a[19] ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 2m bytes l_a[19] ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 2.2.2 bus cycle waveforms a1 a2 a3 a3+1 a3+2 a3+3 a4 a4+1 a4+2 a4+3 a5 a6 d2 d3+1 d3+2 d3+3 d4 d4+1 d4+2 d4+3 d5 d6 d1 d3 l_clk l_adsc# l_cs# l_a[19:2] l_we[3:0]# l_bwe[3:0]# l_oe[3:0]# l_d[31:0] (wr) l_d[31:0] (rd) typical local memory access operations note: refer to manufacturer?s data sheet for detailed timing parameters.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 15 rev. 4.5 ? february 1999 2.3 management bus interface t supports various industry standard micro- processors i n cluding: intel 186/486 family or equivalent motorola mpc series embedded proce s sors t easily adapts to other industry standard cpus t provides separate address and data bus t supports big & little endian byte ordering t supports 16- or 32-bit data bus t provides a single interrupt signal to switch manager cpu 2.3.1 pin description symbol type name & functions p_c[4:0] cmos i n put processor configuration bit [4:0] : ? during the reset cycle, the p_ c[4:0] pins provides the pro c - essor configuration. by using external weak pull-up or -down resistors, they define the external management bus interface configuration. these inputs are sampled at the trailing edge of the reset cycle. c[0] ? defines the cpu clock input is 1x or 2x clock c[1] ? selects either big or little endian byte ordering c[2] ? defines the polarity of the p_rwc (rd/ wr control) input c[3] ? defines the cpu data bus width ? 16-bit or 32-bit c[4] ? defines the timing relationship between p_rdy and p_d[15:0] valid. if c[4] is high, the p_d[15:0] are valid along in the same clock period as p_rdy is asserted. if c[4] is low, the p_rdy is asserted one clock period early ahead of the p_d[15:0] are valid. c[0] c[1] c[2] c[3] c[4] cpu clock byte order rwc bus width rdy timing lo 1x clock little e n dian p_r/w# 16-bit normal hi 2x clock big endian p_w/r# 32-bit early after reset, these pins are used as xpressflow bus data bit [31:27]. p_a[11:1] ttl in (5vt) address bus bit [11:1] ? i/o port address p_d[15:0] ttl i/o-ts (5vt) data bus bit [15:0] ? a 16-bit synchronous data bus. p_ads# ttl in (5vt) address strobe ? indicates valid address is on the bus p_rwc ttl i n - put (5vt) read/write control ? indicates the current bus cycle is a read or write cycle. c[1] defines the polarity of this signal during the reset cycle. c[1]=low p_r/w# is used for powerpc or other similar processors. c[1]=high p_w/r# is used for 386, 486 or other similar processors p_rdy# ttl out- od data ready ? timing indicates for bus data valid p_bs16# ttl out-od bus size 16 ? response to bus master that the sc-201 only supports 16-bit data bus width. p_cs# ttl in (5vt) chip select ? indicates the xpressflow engine is the target for the cu r rent bus operation. p_int ? ttl ou t - put interrupt request to switch manager cpu the polarity of this signal output is programmable via chip configuration register . p_rstin# ttl in-st (5vt) power up reset input ? asynchronous reset input from either power-up reset circuit or from switch ma n ager cpu (except 386) p_rstout cmos output synchronous reset output ? synchronous reset output for i386 family as the switch manager cpu p_clk ttl in (5vt) cpu clock ? 1x clock for the others note: ? output signal with pr o grammable polarity.
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 16 rev. 4.5 ? february 1999 2.3.2 motorola mpc801 processor interface p_clk {clkout} p_ads# {ts#} p_a[11:1] {a[20:30]} p_cs# p_rwc {rd/wr#} p_rdy# {ta#} p_d[31:0] {d[0:31]} p_d[31:0] {d[0:31]} (out) (in) note: mnemonics within {} are the equivalent signals defined by mpc801 typical motorola mpc801 cpu i/o access operations 2.3.3 intel 486 processor interface p_clk p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[31:0] (in) p_d[31:0] (out) typical 486 cpu i/o access operations
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 17 rev. 4.5 ? february 1999 2.3.4 intel 386 processor interface ph2 p_clk ph2 (internal) p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[15:0] (in) p_d15:0] (out) typical 386 cpu i/o access operations ph2 ph1 ph2 or ph1 ph2 p_clk ph2 (internal) p_rstin# p_rstout# internal ph2 clock synchronization note: see intel 386 processor data book for more details
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 18 rev. 4.5 ? february 1999 2.3.5 register map note: all 32-bit registers are d-word aligned. all 16-bit registers are also d-word aligned and right justified. for the little endian cpus, register offset bit [1,0] are always set to be 00. for the big endian cpus, register offset bit [1,0] are always set to be 10. this is a global register. cpu is allowed to write the global register of all devices by a single operation. these registers are reserved for system diagnostic usage only. i/o offset regi s ter description little endian big endian reg. size w/r note: device configuration registers (dcr) gcr global control register hf00 hf02 16-bit w/-- dcr0 device status register hf00 hf02 16-bit --/r dcr1 signature & revision register hf10 hf12 16-bit --/r dcr2 id register hf20 hf22 16-bit w/r dcr3 local control register hf30 hf32 16-bit w/r dcr4 interface status register hf40 hf42 16-bit --/r dcr5 bus credit register hf50 hf52 16-bit w/r interrupt controls isr interrupt status register ? unmasked hf80 hf82 16-bit --/r isrm interrupt status register ? masked hf90 hf92 16-bit --/r imsk interrupt mask register hfa0 hfa2 16-bit w/r iar interrupt acknowledgment register hfb0 hfb2 16-bit w/-- buffer memory inte r face mwar memory write address register ? single c y cle he08 he08 32-bit w/r mrar memory read address register ? single c y cle he18 he18 32-bit w/r mbar memory address register ? burst mode he28 he28 32-bit w/r mwbs memory write burst size (in d-words) he40 he42 16-bit w/r mrbs memory read burst size (in d-words) he50 he52 16-bit w/r mwdr memory write data register he68 he68 32-bit w/-- mwdx memory write data register ? byte swa p ping he6c he6c 32-bit w/-- mrdr memory read data register he68 he68 32-bit --/r mrdx memory read data register ? byte swa p ping he6c he6c 32-bit --/r buffers & stacks management frame control buffers fcbba frame control buffer ? base address hd00 hd02 16-bit w/r fcba frame control buffer ? buffer alloc a tion hd20 hd22 16-bit --/r fcbr frame control buffer ? buffer release hd20 hd22 16-bit w/-- fcbag frame control buffer ? buffer aging status hd30 hd32 16-bit --/r fcbsa frame ctrl buffer stack ? base a d dress hd80 hd82 16-bit w/r fcbsl frame ctrl buffer stack ? size limit hd90 hd92 16-bit w/r fcbst frame ctrl buffer stack ? buffer low threshold hda0 hda2 16-bit w/r fcbss frame ctrl buffer stack ? allocation status hdb0 hdb2 16-bit --/r
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 19 rev. 4.5 ? february 1999 i/o offset regi s ter description little endian big endian reg. size w/r note: buffers & stacks management (continue) switch control buffers scbba switch control buffer ? base address hc00 hc02 16-bit w/r scba switch control buffer ? buffer alloc a tion hc20 hc22 16-bit --/r scbag switch control buffer ? buffer aging status hc30 hc32 16-bit --/r scbsa switch ctrl buffer stack ? base a d dress hc80 hc82 16-bit w/r scbsl switch ctrl buffer stack ? size limit hc90 hc92 16-bit w/r scbst switch ctrl buffer stack ? buffer low threshold hca0 hca2 16-bit w/r scbss switch ctrl buffer stack ? allocation status hcb0 hcb2 16-bit --/r mac control tables mcta mac control table ? table allocation hb20 hb22 16-bit --/r mctr mac control table ? table release hb20 hb22 16-bit w/- mctsa mac ctrl table stack ? base a d dress hb80 hb82 16-bit w/r mctss mac ctrl table stack ? allocation status hbb0 hbb2 16-bit --/r queue management qsba queue structure ? base address ha00 ha02 16-bit w/r mfta multicast frame table ? base a d dress ha10 ha12 16-bit w/r cinq cpu input queue ha88 ha88 32-bit w/-- cotq cpu output queue ha88 ha88 32-bit --/r csq0 cpu status queue ? 1 st d-word ha98 ha98 32-bit --/r csq1 cpu status queue ? 2 nd d-word haa8 haa8 32-bit --/r csq2 cpu status queue ? 3 rd d-word hab8 hab8 32-bit --/r cam i n terface ccwr cam command/data write register h908 h908 32-bit w/-- csrl cam status/data read register low h928 h928 32-bit --/r csrh cam status/data read register high h938 h938 32-bit --/r hisc control hpcr hisc processor control register h980 h982 16-bit w/r hmcl hisc micro-code loading port h998 h998 32-bit w/r hprc hisc priority control register h9b0 h9b2 16-bit w/r
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 20 rev. 4.5 ? february 1999 2.4 xpressflow bus interface t vertex networks? optimized xpressflow bus archite c ture t provides 1g bps switching bandwidth t full multi bus master structure t allows xpressflow engine to communicate with access controllers via a message pas s - ing protocol command messages for passing control info r mation between devices data messages for forwarding an ethernet frame from receiving port to transmission port t built-in intelligent bus load regulator for data traffic ba l ancing t provides centralized bus arbitration with two level request priorities high priority for data messages low priority for command messages 2.4.1 pin description sy m bol type name & functions s_d[31:0] cmos i/o-ts data bus bit [31:0] ? a 32-bit synchronous data bus. note: during the system reset period, data bit [31:28] are used as processor inte r face configuration bit [0:3] s_msgen# cmos i/o-ts message envelope ? encompasses the entire period of a message transfer. targets use the leading edge of this signal to detect the b e - ginning of a message transfer, and to decode the message header for the intended ta r get(s). s_eof# cmos i/o-ts end of frame ? only used by frame data transfer messages to identify the end of frame condition. this signal is synchronous with the rx frame status word a p pended to the end of the message. s_irdy cmos i/o-ts initiator ready ? a normal true signal. when negated, it indicates the initiator had asserted wait state(s) in between command words. target should use this signal as enable signal for latching the data from the bus. s_tabt# cmos i/o-od target abort ? when asserted, the target had aborted the reception of current message on the bus. s_hpreq# cmos i/o-od high priority request ? indicates one or more bus requester is r e - questing for high priority message tran s fer. s_req[8:1]# cmos input bus request [8:1] ? bus request signals from access controllers to bus access arbitrator in xpressflow engine s_gnt[8:1]# cmos ou t put bus grant [8:1] ? bus grant signals from bus arbitrator to bus r e - questers s_ovld# cmos ou t put bus overload ? when asserted all data forwarding bus bandwidth has been allocated. cannot support additional load for data forwarding tra f - fic s_clk cmos input xpressflow bus clock ? 33mhz system clock
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 21 rev. 4.5 ? february 1999 2.4.2 bus cycle waveforms c0 d5 eof d2 c1 d0 d1 d3 d4 s_clk s_msgen# s_d[31:0] s_eof# s_irdy xpressflow bus data transfer cycle command cycle data xfer w/o data c0 c1 c0 c1 eof c1 c0 aborted command s_clk s_msgen# s_d[31:0] s_eof# s_tabt# other xpressflow bus cycles s_clk s_req[k]# s_req[j]# s_hpreq# high priority request pre-empts the low priority request
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 22 rev. 4.5 ? february 1999 s_clk s_msgen# s_req[j]# s_gnt[j]# s_hpreq# s_req[i]# s_gnt[i]# xpressflow bus arbitration s_clk s_req[k]# s_ovld# bus overload pre-empts the data transfer request 2.5 test pins sy m bol type name & functions test cmos i/o test mode selection & test output ? set test mode upon reset, and provides test status output during test mode
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 23 rev. 4.5 ? february 1999 3 dc specification 3.1 absolute maximum ratings storage temperature -65 c to +150c operating temperature 0c to +70c supply voltage v dd with respect to v ss +3.0 v to +3.6 v voltage on 5v tolerant input pins -0.5 v to (v dd + 2.5 v) voltage on other pins -0.5 v to (v dd + 0.3 v) stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r e liability. 3.2 dc characteristics v dd = 3.0 v to 3.6 v; t ambient = 0c to +70c preliminary sy m bol parameter description min typ max unit f osc frequency of operation ( -40) 20 40.0000 mhz frequency of operation ( -50) 20 50.0000 mhz frequency of operation (-66) 20 66.6666 mhz i dd supply power ? @ 33.3333 mhz (v dd =3.3 v) 300 500 ma supply power ? @ 40 mhz (v dd =3.3 v) 300 500 ma supply power ? @ 50 mhz (v dd =3.3 v) 300 500 ma v oh-cmos output high voltage (cmos) i oh = -1.0 ma v dd - 0.5 v v ol-cmos output low voltage (cmos) i ol = 1.0 ma 0.45 v v oh-ttl output high voltage (ttl) i oh = -1.0 ma 2.4 v v ol-ttl output low voltage (ttl) i ol = 1.0 ma 0.45 v v ih-cmos input high voltage (cmos) vdd x 70% v dd + 0.3 v v il-cmos input low voltage (cmos) -0.5 vdd x 30% v v ih-ttl input high voltage (ttl) 2.0 v dd + 0.3 v v il-ttl input low voltage (ttl) -0.3 +0.8 v v ih-5vt input high voltage (ttl 5v tolerant) 2.0 v dd + 2.5 v v il-5vt input low voltage (ttl 5v tolerant) -0.3 +0.8 v i li input leakage current (0.1 v v in v dd ) (all pins except those with internal pull- up/pull-down r e sistors) 10 a i lo output leakage current (0.1 v v out v dd ) 15 a i ih input leakage current v ih = v dd - 0.1 v (pins with internal pull-down resistors) 60 a i il input leakage current v il = 0.1 v (pins with internal pull-up resistors) -60 a c in input capacitance 8 pf c out output capacitance 8 pf c i/o i/o capacitance 10 pf
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 24 rev. 4.5 ? february 1999 4 ac specification 4.1 xpressflow bus interface: s1-min s1-max s2-min s2-max s3-min s3-max s4-min s4-max s6-min s6-max s7-min s7-max s8-min s8-max s9-min s9-max s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_gnt[7:0]# s_ovld# xpressflow bus interface ? output valid delay timing s1-min s12 s2-min s13 s3-min s14 s4-min s15 s_clk s_d[31:0] s_msgen# s_eof# s_irdy xpressflow bus interface ? outpu t float delay timing s17 s19 s21 s23 s27 s29 s31 s18 s20 s22 s24 s28 s30 s32 s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_req[7:0]# xpressflow bus interface ? input setup and hold timing
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 25 rev. 4.5 ? february 1999 -40 -50 -66 sy m bol parameter min ( ns) max ( ns) min ( ns) max ( ns) min ( ns) max ( ns) note: s1 s_d[31:0] output valid delay 6 14 5 11 4 8.5 c l = 50pf s2 s_msgen# output valid delay 6 14 5 11 4 8.5 c l = 50pf s3 s_eof# output valid delay 6 14 5 11 4 8.5 c l = 50pf s4 s_irdy output valid delay 6 14 5 11 4 8.5 c l = 50pf s6 s_tabt# output valid delay 6 14 5 11 4 8.5 c l = 50pf s7 s_hpreq# output valid delay 6 14 5 11 4 8.5 c l = 50pf s8 s_gnt[7:0]# output valid delay 6 14 5 11 4 8.5 c l = 20pf s9 s_ovld# output valid delay 6 14 5 11 4 8.5 c l = 50pf s12 s_d[31:0] output float delay 18 15 12 s13 s_msgen# output float delay 18 15 12 s14 s_eof# output float delay 18 15 12 s15 s_irdy output float delay 18 15 12 s17 s_d[31:0] input set-up time 2 1.5 1 s18 s_d[31:0] input hold time 5.5 4.5 3.5 s19 s_msgen# input set-up time 2 1.5 1 s20 s_msgen# input hold time 5.5 4.5 3.5 s21 s_eof# input set-up time 2 1.5 1 s22 s_eof# input hold time 5.5 4.5 3.5 s23 s_irdy input set-up time 2 1.5 1 s24 s_irdy input hold time 5.5 4.5 3.5 s27 s_tabt# input set-up time 5.5 4.5 3.5 s28 s_tabt# input hold time 5.5 4.5 3.5 s29 s_hpreq# input set-up time 4.5 3.5 2.5 s30 s_hpreq# input hold time 5.5 4.5 3.5 s31 s_req[7:0]# input set-up time 6 5 4 s32 s_req[7:0]# input hold time 5.5 4.5 3.5 ac characteristics -- xpressflow bus interface
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 26 rev. 4.5 ? february 1999 4.2 cpu bus interface: p16-min p15 p_clk p_d[31:0] cpu bus interface ? outpu t float delay timing p16-min p16-max p17-min p17-max p18-min p18-max p_clk p_d[31:0] p_rdy# p_int cpu bus interface ? output valid delay timing p1 p3 p5 p7 p9 p11 p2 p4 p6 p8 p10 p12 p_clk p_rst# p_ads# p_w/r# p_cs# p_a[11:1] p_d[31:0] cpu bus interface ? input setup and hold timing -40 -50 -66 symbol parameter min ( ns) max ( ns) min ( ns) max ( ns) min ( ns) max ( ns) note: p1 p_rst# input setup time 13 10 8 p2 p_rst# input hold time 3.5 2.5 2 p3 p_ads# input set-up time 13 10 8 p4 p_ads# input hold time 3.5 2.5 2 p5 p_w/r# input set-up time 13 10 8 p6 p_w/r# input hold time 3.5 2.5 2 p7 p_cs# input set-up time 13 10 8 p8 p_cs# input hold time 3.5 2.5 2 p9 p_a[11:1] input set-up time 13 10 8 p10 p_a[11:1] input hold time 3.5 2.5 2 p11 p_d[31:0]# input set-up time 13 10 8 p12 p_d[31:0]# input hold time 3.5 2.5 2 p15 p_d[31:0]# output float delay 17 13 10 p16 p_d[31:0]# # output valid delay 17 13 10 c l = 60pf p17 p_rdy# output valid delay 13 10 8 c l = 60pf p18 p_int# output valid delay 8.5 6.5 5 c l = 20pf ac characteristics -- cpu bus interface
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 27 rev. 4.5 ? february 1999 4.3 local memory interface: local memory interface: l1 l2 l_clk l_d[31:0] local memory interface ? input setup and hold timing l3-min l10 l_clk l_d[31:0] local memory interface ? output float delay timing l3-min l3-max l4-min l4-max l5-min l5-max l6-min l6-max l7-min l7-max l8-min l8-max l9-min l9-max l_clk l_d[31:0] l_a[19:2] l_cs[3:0]# l_adsc# l_bwe[3:0]# l_we#] l_oe# local memory interface ? output valid delay timing -40 -50 -66 symbol parameter min ( ns) max ( ns) min ( ns) max ( ns) min ( ns) max ( ns) note: l1 l_d[31:0]# input set-up time 6.5 5.5 4 l2 l_d[31:0]# input hold time 3 2.5 2 l3 l_d[31:0]# output valid delay 5 17 4 13 3 10 c l = 30pf l4 l_a[19:2] output valid delay 5 17 4 13 3 10 c l = 30pf l6 l_adsc# output valid delay 5 17 4 13 3 10 c l = 30pf l7 l_bwe[3:0]# output valid delay 5 17 4 13 3 10 c l = 30pf l8 l_we# output valid delay 5 17 4 13 3 10 c l = 10pf l9 l_oe# output valid delay 5 17 4 13 3 10 c l = 10pf l10 l_d[31:0]# output float delay 22 18 14 ac characteristics ? local memory interface
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 28 rev. 4.5 ? february 1999 4.4 cam memory interface: c1 c3 c5 c2 c4 c6 s_clk c_d[15:0] c_mf# c_ff# cam memory interface ? input setup and hold timing c7-min c12 s_clk c_d[15:0] cam memory interface ? output float delay timing c7-min c7-max c8-min c8-max c9-min c9-max c10--min c10-max c11-min c11-max s_clk c_d[15:0] c_ce# c_we# c_cm# c_ec# cam memory interface ? output valid delay timing -40 -50 -66 symbol parameter min ( ns) max ( ns) min ( ns) max ( ns) min ( ns) max ( ns) note: c1 c_d[15:0]# input set-up time 4.5 4 5 c2 c_d[15:0]# input hold time 1.5 1.5 2 c3 c_mf# input set-up time 4.5 4 5 c4 c_mf# input hold time 1.5 1.5 2 c5 c_ff# input set-up time 4.5 4 5 c6 c_ff# input hold time 1.5 1.5 2 c7 c_d[15:0]# output valid delay 5 18 4 15 6 20 c8 c_ce# output valid delay 5 18 4 15 6 20 c9 c_we# output valid delay 5 18 4 15 6 20 c10 c_cm# output valid delay 5 18 4 15 6 20 c11 c_ce# output valid delay 5 18 4 15 6 20 c12 c_d[16:0]# output float delay 13 10 15 ac characteristics ? cam memory interface
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine ? 1998 vertex networks, inc. 29 rev. 4.5 ? february 1999 5 packaging information 5.1 256-pin pqfp a 30.6 0.20 25.2 ref 28.0 0.20 pin 1 i.d. 25.2 ref 28.0 0.20 30.6 0.20 0.40 typ 0.14/0.22 128 129 192 193 256 1 64 d b 65 3.40 0.20 0.25 min. 4.10 max. 1.30 ref. 0.50/0.75 c
preliminary information xpressflow-2020 series ? sc220 ethernet switch chipset xpressflow engine this document contains preliminary information on our product. vertex reserves the right to make any changes without notice. 1998 v ertex n etworks 16842 von karman ave, suite 250 irvine, ca 92606 -4950 rev. 4.5- february, 1999 tel. 1-714-252-8880, fax: 1-714-252-8868 web site: www.vertex-networks.com 5.2 256- pin bga ordering information part number description identification vertex networks use revision sc220 xpressflow switch engine c 0 b tav rrr environmental ? c = commercial revision - 001 = rev.1 i = industrial for latest revision, leave blank speed grade - 0 = 40 mhz 5 = 50 mhz 6 = 66 mhz package - b = bga p= pqfp a b 27.00 pin 1 i.d. a b c d e f g h j k l m n p r t u v w y 2.50 max 0.50 / 0.70 c 24.13 1.27 2 4 1 3 6 8 5 7 10 12 9 11 20 19 18 17 14 16 13 15
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: dimension conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 27.20 26.80 24.00 ref 256 1.27 0.60 0.90 24.00 ref 1.17 ref 26.80 min 0.50 2.20 27.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls are defined by the spherical crowns of the solder balls. 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 3. primary datum -c- and seating plane 5. not to scale. d e e1 d1 e a a1 a2
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: 3. the top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 1. pin 1 indicator may be a corner chamfer, dot or both. 2. controlling dimensions are in millimeters. 4. dimension d1 and e1 do not include mould protusion. notes: pin 1 index corner e1 e d d1 l a1 a2 a = 0-7
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